To have both high efficiency and linearity in power amplifiers linearization techniques should be used. One structure with the ability of cancelling the inherent limitations of the LINC linearization techniques is proposed in this article. The gain and phase imbalances in LINC technique has been compensated using optimization algorithms. According to the analysis a feedback path has been added in the conventional LINC transmitter that calibrates any phase and gain mismatches adaptively; using optimization algorithms. Many simulations have been performed to validate the structure functionality and extracted relations. In this paper M68749 power amplifier is used at 390MHz frequency with output power of 5 watt. Simulations show that power spectral density of proposed architecture has 40dB/Hz improvement in spreading to adjacent channels.

A new output structure for class E power amplifier (PA) is proposed in this paper. A series LC resonator circuit, tuned near the second harmonic of the operating frequency is added to the output circuit. This resonator causes low impedance at the second harmonic. The output circuit is designed to shape the switch voltage of the class E amplifier and lower the voltage stress of the transistor. The maximum switch voltage of the conventional class E PA is 3.56Vdc. However, higher switch voltage of about 4.5VDC may be occurred, by considering nonlinear drain-to-source capacitance in class E PA. The obtained peak switch voltage of the designed class E PA is approximately 75% of the conventional one with the same conditions, which shows a significant reduction in peak switch voltage. MOSFET parasitic nonlinear gate-to-drain and nonlinear drain-to-source capacitances of the MOSFET body junction diode also affect the switch voltage in class E PA, which are considered in this paper. The actual MOSFETs have these parasitic capacitances; therefore, it is necessary to consider these elements in the design procedure. Reduced switch voltage in class E PA relaxes the breakdown voltage constraints of the active device. In the switch voltage of the designed circuit, the zero voltage and zero derivative switching (ZVS and ZVDS) conditions are satisfied. Simulation of the presented circuit is performed using PSpice and LTspice softwares. For verification of the designed circuit, the presented PA is fabricated and measured.

Background and Objectives: In this paper, a novel structure as a Folded-Mirror (FM) Trans-impedance Amplifier (TIA) is designed and introduced for the first time based on the combination of the current-mirror and the folded-cascade topologies. The trans-impedance amplifier stage is the most critical building block in a receiver system. This novel proposed topology is based on the combination of the current mirror topology and the folded-cascade topology, which is designed using active elements. The idea is to use a current mirror topology at the input node. In the proposed circuit, unlike many other reported designs, the signal current (and not the voltage) is being amplified till it reaches the output node. The proposed TIA benefits from a low input resistance, due to the use of a diode-connected transistor, as part of the current mirror topology, which helps to isolate the dominant input capacitance. So, as a result, the data rate of 5Gbps is obtained by consuming considerably low power. Also, the designed circuit employs only six active elements, which yields a small occupied chip area, while providing 40.6dBΩ of trans-impedance gain, 3.55GHz frequency bandwidth, and 664nArms input-referred noise by consuming only 315µW power using a 1V supply. Results justify the proper performance of the proposed circuit structure as a low-power TIA stage.Methods: The proposed topology is based on the combination of the current mirror topology and the folded-cascade topology. The circuit performance of the proposed folded-mirror TIA is simulated using 90nm CMOS technology parameters in the Hspice software. Furthermore, the Monte-Carlo analysis over the size of widths and lengths of the transistors is performed for 200runs, to analyze the fabrication process.Results: The proposed FM TIA circuit provides 40.6dBΩ trans-impedance gain and 3.55GHz frequency bandwidth, while, consuming only 315µW power using a 1V supply. Besides, as analyzing the quality of the output signal in the receiver circuits for communication applications is vital, the eye-diagram of the proposed FM TIA for a 50µA input signal is opened about 5mV, while, for a 100µA input signal the eye is opened vertically about 10mV. So, the vertical and horizontal opening of the eye is clearly shown. Furthermore, Monte-Carlo analysis over the trans-impedance gain represents a normal distribution with the mean value of 40.6dBΩ and standard deviation of 0.4dBΩ. Also, the value of the input resistance of the FM TIA is equal to 84.4Ω at low frequencies and reaches the value of 75Ω at -3dB frequency. The analysis of the effect of the feedback network on the value of the input resistance demonstrates the input resistance in the absence of the feedback network reaches up to 1.4MΩ, which yields the importance of the existence of the feedback network to obtain a broadband system.Conclusion: In this paper, a trans-impedance amplifier based on a combination of the current-mirror topology and the folded-cascade topology is presented, which amplifies the current signal and converts it to the voltage at the output node. Due to the existence of a diode-connected transistor at the input node, the input resistance of the TIA is comparatively small. Furthermore, four out of six transistors are PMOS transistors, which represent less thermal noise in comparison with NMOS transistors. Also, the proposed Folded-Mirror topology occupies a relatively small area on-chip, due to the fact that no passive element is used in the feedforward network. Results using 90nm CMOS technology parameters show 40.6dBΩ trans-impedance gain, 3.55GHz frequency bandwidth, 664nArms input-referred noise, and only 315µW power dissipation using a 1volt supply, which indicates the proper performance of the proposed circuit as a low-power building block.

The use of smart radio equipment with high performance is one of the requirements of the smart police, and in this regard, it is necessary to consider operational requirements in the design of different parts of the radio transmitter and receiver. In the transmitter section, the power amplifier has some features such as power consumption, output power, and power added efficiency which are significant items in the design. This paper deals with the design of high- performance Class-E power amplifiers for the Radio communication systems. For this purpose, a cascade structure consisting of an amplifier is used as a switch to amplify the signal and an amplifier to increase reliability. In this circuit, one transistor is biased in the triode region as a switch and the other transistor is biased in the triode or saturation region. In this paper, a cascade class E power amplifier with a driver circuit and a compensator circuit is proposed to increase the output power and power added efficiency (PAE). The presented PA in this paper is appropriate for Radio communication. In this paper, the output power and PAE is improved by changing the structure of the PA. The PA has 2.6 GHz operating frequency, output power of 31.4 dBm, maximum PAE of 55.5%. The designed circuits are simulated with Cadence software.

This paper presents a new extended high-efficiency range Doherty amplifier. This amplifier uses a main and only a single auxiliary amplifier. In order to increase efficiency and extend the output high-efficiency range, asymmetrical cells are employed as the main and auxiliary amplifiers in class-F harmonic termination complex combining load (CCL) methodology. To verify the proposed methodology, a Doherty Power Amplifier (DPA) with 12 dB output back-off (OBO) is designed and fabricated for wideband code division multiple access (WCDMA) applications. Large signal continuous wave measurement results show the power gain of about 10. 9 dB with a drain efficiency of 66 % at 12 dB of OBO. A two-tone test exhibits a third-order intermodulation distortion (IMD) of lower than-21. 5 dBc. Modulated wave measurements show over 56. 5 % of average drain efficiency and an adjacent channel leakage power ratio (ACLR) of lower than-26. 5 dBc at an output power level of 31. 5 dBm.

One of the most important parts of communication systems are matching networks. If the matching networks are not broadband, no matter how good the rest of the communication system is, the system’s bandwidth is bounded by matching network. In this project, we explain the real frequency technique and use it to design and simulate a broadband matching network for use in a broadband power amplifier. The designed prototype operates from 0. 1 up to 4 GHz with around 12 dB power gain and delivers approximately 40 dBm or 10 Watts of power. The power added efficiency of the device more than 47% in the wide operation bandwidth. CGH40010F GaN HEMT device of Wolfspeed-Cree Company is used in the design.

This paper offers a modified circuit for improving linearization of power amplifier with based on the model of the Feed Forward circuit amplifier. With the help of mathematical model for the single power amplifier, the circuit is simulated und a demonstrator is built and measured. it is used a complex Taylor series for modeling the power amplifier by the approximation of the amplitude transfer function and the level-dependence of the transmission-phase of the power amplifier and can be understood as a simplified form of Volterra series. In our proof of concept experiment, we verified the concept but also found that the adjustment of the circuit is critically dependent on the drive conditions and linearization is achieved only for a narrow range of drive power. The simulation of the total circuit is largely determined by the models for the transmission characteristics of the two power amplifiers. The new circuit in compare with the conventional Feed Forward amplifier, in addition a significant increase in efficiency to minimize the power of the distortion signal 3IMD for large driving amplitude (large signals).

A digital look-up table adaptive predistortion technique using a six-port receiver for power amplifier linearization is presented. The system is designed in Ka-band for a DVB-S2 satellite link. We use a six-port receiver at the linearization loop in place of classic heterodyne receivers. The six-port receiver is implemented by the use of passive microwave circuits and detector diodes. This approach highly reduces cost and complexity of the linearization system. The fabrication results of a five-port receiver operating in 23-29 GHz is presented in this paper. The simulation results confirm suitability of using this architecture in the power amplifier linearization loop. The third order intermodulation products and the fifth order intermodulation products reduce about 43 dB and 25 dB respectively, after linearization of the power amplifier. The resulting spectrum of the output signal shows significant reduction of the intra-system interference to the adjacent networks which is mainly due to the nonlinearity effects of the power amplifier.

The graphical technique for nonlinear circuits was described that enable us to optimize circuits to obtain maximum output power, maximum efficiency or minimum intermodulation.According to this method a high power amplifier in the Ka band was designed. Using a nonlinear model of the transistor, optimum slope for load-line was determined so that maximum power at the output was obtainable, then the output matching circuit was synthesized. Finally, the nonlinear network of the high power amplifier was analyzed by the harmonic balance method and the output load cycles were optimized by modification of the bias point or output matching network.

In this paper, a low power 2×3 matrix distributed amplifier (DA) with tapper transmission lines is introduced in 180 nm CMOS technology. The matrix structure is used to provide the mechanisms of multiplication and additive of the current for increasing the gain and reducing the power consumption. In the input stage, a controllable cascade gain cell is used to expand the bandwidth and remove to need the additional capacitors in the input gate and central transmission lines. Moreover, the terminating resistor of the input gate transmission line is replaced with an RL network. The proposed distributed amplifier is designed and simulated using TSMC 0.18 µm CMOS technology in Cadence Spectre-RF over the frequency of 1-30 GHz. Operated at 1 V, the proposed DA consumes 25.16 mW. Simulation results show that the proposed DA achieves a direct power gain (S21) of 12±1 dB with an average NF of 5.75 dB and average IIP3 of -6.11 over the 1–24 GHz band of interest. The input and output return losses are also more than 10 dB.